Features
 | differential and single ended working mode |
| rectification amplifier up to 10 GHz |
| rise and fall time of 30 ps |
| binary clock divider up 10 GHz input frequency |
| divider factor is settable from 128 to 1024 |
| single power supply of –5 V |
Applications
| pre-divider in PLL circuits |
| signal rectification |
| clock recovery |
| conversion single ended to differential |
| conversion differential to single ended |
|
Description The
MEO-0801A is a ultra high speed clock divider based on a 0.8 µm SiGe-HBT process. It
consist of a differential input amplifier, a programmable divider and output buffers. The
device is prepared for working in a 50 W environment. The device provides a differential input and differential
outputs. All ports can be used for single ended operations matched to 50 W environment.
The divider based on asynchronous switched flip-flops. The divider
output is resynchronised to the input clock.
It is available mounted on a thin film carrier. |
